In a typical TAB process, semiconductor chips are machine-positioned at die sites on a reel-to-reel tape which carries a pre-formed conductive pattern at each die site. The leads which extend from each chip are gang-bonded to the conductive pattern at the die site where the chip has been positioned. Efficiency of production and lower cost for high volume applications are among the goals of the TAB process.
To illustrate some of the problems associated with conventional TAB processes, two typical semiconductor structures, each resulting from a different TAB process, will be described briefly.
Turning first to the semiconductor structure shown in FIGS. 1 and 2, a conventional "tape pak" device 10 is shown. This device includes an integrated circuit chip 12 whose leads have been bonded to beam leads 14. The beam leads 14 are part of a metallized, conductive pattern that is formed on a single-layer metal tape 16. Sprocket holes 18 in the tape 16 permit the tape to be automatically indexed from one work station to another.
A rigid, molded support ring 20 encloses the illustrated die site to add rigidity to the overall structure during testing and burn-in procedures. Also, the chip 12 itself is encapsulated (as indicated by the reference numeral 22) with the same molding compound that is used to form the support ring 20.
Although the illustrated semiconductor structure is advantageous for some applications, it does have drawbacks. One disadvantage is that the protective encapsulation around the chip 12 prohibits making electrical connection to the bottom surface of the chip, as is needed in cases such as when the bottom surface of a microprocessor chip needs to be coupled to ground potential.
A second drawback is that the molding process which encapsulates the chip 12 and forms the support ring 20 slows down the TAB process and, therefore, adds to the cost. Moreover, encapsulation of the chip 12 makes it difficult to transfer heat out of the chip.
Another conventional semiconductor structure formed by a TAB processes is shown in FIG. 3. This structure, shown in cross-section, includes an integrated circuit chip 24 whose leads 26 are bonded to beam leads 28 which are part of a metallized, conductive pattern on a continuous, two-layer tape. The top layer is a metal foil in which the pattern of beam leads is formed. The bottom layer of this tape is typically a plastic film that has been patterned to form a support ring 30 which surrounds the chip 24 to provide support for the beam leads 28. Another portion 32 of the plastic film underlies the outer ends of the beam leads 28. A protective encapsulating material 34 (epoxy, for example) covers at least the top surface of the chip 24.
The illustrated structure is tested by probing test areas 36 near the outer ends of the beam leads 28. Upon completion of the test, the outer ends of the leads 28 are excised along with the plastic film portions 32, as by cutting along the dotted lines 38 and 40. Thereafter, the beam leads are formed and bonded to a substrate (not shown).
The tape used in the structure of FIG. 3 is at least a two-layered tape comprising a top layer of metal (such as copper foil) and a bottom layer of plastic film. In some applications, such a structure requires a third, intermediate layer of adhesive between the layers of metal and plastic film.
There are several aspects of the structure shown in FIG. 3 that contribute to an undesirably high cost: the use of a two or three-layered tape; the requirement for a support ring; and a separate step to provide the protective coating over the chip.